View CS5308GDWR28_3901739.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2006 july, 2006 ? rev. 6 1 publication order number: cs5308/d cs5308 two?phase pwm controller with integrated gate drivers for vrm 8.5 the cs5308 is a second ? generation, two ? phase step down controller that incorporates all control functions required to power next generation processors. proprietary multi ? phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. enhanced v 2 ? control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. the cs5308 is a second generation pwm controller because it optimizes transient response by combining traditional enhanced v 2 with an internal pwm ramp and fast ? feedback directly from v core to the internal pwm comparator. these enhancements provide greater design flexibility, facilitate use and reduce output voltage jitter. the multi ? phase architecture reduces input and output filter ripple, allowing for a significant reduction in filter size and inductor values with a corresponding increase in the output inductor current slew rate. this approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost. the cs5308 includes vtt monitoring and timing, vtt power good (vtt pgd ), power good (pwrgd), and internal mosfet gate drivers to provide a ?fully integrated solution? to simplify design, minimize circuit board area, and reduce overall system cost. features ? enhanced v 2 control method ? internal pwm ramp ? fast ? feedback directly from v core ? 5 ? bit dac with 1% tolerance ? adjustable output voltage positioning ? 200 khz to 800 khz operation set by resistor ? current sensed through sense resistors or output inductors ? adjustable hiccup mode current limit ? overvoltage protection through synchronous mosfets ? individual current limits for each phase ? on ? board current share amplifiers ? 3.3 v, 1.0 ma reference output ? vtt monitoring and vtt power good (vtt pgd ) ? v core power good ? on/off control (through comp pin) ? improved noise immunity http://onsemi.com device package shipping ordering information cs5308gdw28 so ? 28l 27 units/rail CS5308GDWR28 so ? 28l 1000 tape & reel a = assembly location wl, l = wafer lot yy, y = year ww, w = work week so ? 28l dw suffix case 751f marking diagram 1 cs5308 awlyyww 28 1 28 pin connections 1 28 v ccl12 v id1 pgnd v id0 gate(l)1 v id25 gate(h)1 i lim v cch1 ref v ccl v drp lgnd v fb r osc comp gate(l)2 v id2 gate(h)2 v id3 vtt pgd cs ref v cch2 pwrgd vtt ct cs1 vtt cs2
cs5308 http://onsemi.com 2 figure 1. application diagram. 5.0 v to 1.7 v at 28 a, 335 khz with 12 v bias for pentium iii applications recommended components: l1: coiltronics ctx15 ? 14771 or t30 ? 26 core with 3t of #16 awg l2: coiltronics ctx22 ? 15401 x1 or t50 ? 52 with 5t of #16 awg bifilar c input : 2 sanyo oscon 6sp680m (680 f, 6.3 v) c out : 7 rubycon 6.3za1000m10x16 (1000 f, 6.3 v) c ceramics : 12 panasonic ecj ? 3yb0j106k (10 f, 6.3 v) q1 ? q4: on semiconductor ntb85n03 (28 v, 85 a) v id25 v id0 v id1 v id2 v id3 pwrgd sig gnd r lim2 1.0 k r lim1 5.76 k c ref 0.1 f r csref 20 k sig gnd c csref 0.01 f cs ref r drp1 11.5 k c fbk2 470 pf v fb c amp 3.9 nf c cmp1 3.3 nf c cmp2 0.1 f sig gnd r osc 39.2 k sig gnd c vcc 1.0 f r 5v 1.0 +5.0 v +12 v cs5308 comp v fb v drp ref i lim v id25 v id0 v id1 v id2 v id3 pwrgd cs ref cs1 cs2 r osc lgnd v ccl v cch1 gate(h)1 gate(l)1 pgnd v ccl12 gate(l)2 gate(h)2 v cch2 vtt pgd vtt ct vtt sig gnd c vtt 0.1 f r vtt 1.0 k c vcch1 1.0 f c vcc12 1.0 f c vcch2 1.0 f c q1 0.1 f q1 q2 gate1 gate2 c q3 0.1 f q3 q4 gate3 gate4 l1 300 nh + c input electrolytics l2 825 nh + c out electrolytics c cer ceramics l3 825 nh swnode1 swnode2 cs1 cs2 r cs1 100 k r cs2 100 k c cs1 0.01 f c cs2 0.01 f r fbk1 6.49 k r cmp1 5.62 k vtt v out
cs5308 http://onsemi.com 3 maximum ratings* rating value unit operating junction temperature 150 c lead temperature soldering: reflow: (smd styles only) (note 1) 230 peak c storage temperature range ? 65 to 150 c package thermal resistance junction ? to ? case, r jc junction ? to ? ambient, r ja 15 75 c/w c/w esd susceptibility (human body model) 2.0 kv jedec moisture sensitivity level 2 ? 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. maximum ratings pin name v max v min i source i sink comp 6.0 v ? 0.3 v 1.0 ma 1.0 ma v fb 6.0 v ? 0.3 v 1.0 ma 1.0 ma v drp 6.0 v ? 0.3 v 1.0 ma 1.0 ma cs1 ? cs2 6.0 v ? 0.3 v 1.0 ma 1.0 ma cs ref 6.0 v ? 0.3 v 1.0 ma 1.0 ma pwrgd 6.0 v ? 0.3 v 1.0 ma 8.0 ma vid pins 6.0 v ? 0.3 v 1.0 ma 1.0 ma i lim 6.0 v ? 0.3 v 1.0 ma 1.0 ma ref 6.0 v ? 0.3 v 1.0 ma 20 ma vtt 6.0 v ? 0.3 v 1.0 ma 1.0 ma vtt ct 6.0 v ? 0.3 v 1.0 ma 40 ma vtt pgd 6.0 v ? 0.3 v 1.0 ma 8.0 ma v cchx 20 v ? 0.3 v n/a 1.5 a for 1.0 s, 200 ma dc gate(h)x 20 v ? 0.3 v dc ? 2.0 v for 100 ns 1.5 a for 1.0 s, 200 ma dc 1.5 a for 1.0 s, 200 ma dc gate(l)x 16 v ? 0.3 v dc ? 2.0 v for 100 ns 1.5 a for 1.0 s, 200 ma dc 1.5 a for 1.0 s, 200 ma dc v ccl12 16 v ? 0.3 v n/a 1.5 a for 1.0 s, 200 ma dc pgnd 0.3 v ? 0.3 v 2.0 a, 1.0 s, 200 ma dc n/a lgnd 0 v 0 v 50 ma n/a v ccl 16 v ? 0.3 v n/a 50 ma r osc 6.0 v ? 0.3 v 1.0 ma 1.0 ma
cs5308 http://onsemi.com 4 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v cch1 = v cch2 < 20 v; 4.5 v < v ccl =v ccl12 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k, c comp = 0.1 f, c ref = 0.1 f, dac code 01000 (1.65 v), c vcc = 0.1 f; unless otherwise specified.) characteristic test conditions min typ max unit voltage identification dac accuracy (all codes) measure v fb = comp ? ? 1.0 % v id25 v id3 v id2 v id1 v id0 ? ? ? ? ? 0 0 1 0 0 ? 1.039 1.050 1.061 v 1 0 1 0 0 ? 1.064 1.075 1.086 v 0 0 0 1 1 ? 1.089 1.100 1.111 v 1 0 0 1 1 ? 1.114 1.125 1.136 v 0 0 0 1 0 ? 1.139 1.150 1.162 v 1 0 0 1 0 ? 1.163 1.175 1.187 v 0 0 0 0 1 ? 1.188 1.200 1.212 v 1 0 0 0 1 ? 1.213 1.225 1.237 v 0 0 0 0 0 ? 1.238 1.250 1.263 v 1 0 0 0 0 ? 1.262 1.275 1.288 v 0 1 1 1 1 ? 1.287 1.300 1.313 v 1 1 1 1 1 ? 1.312 1.325 1.338 v 0 1 1 1 0 ? 1.337 1.350 1.364 v 1 1 1 1 0 ? 1.361 1.375 1.389 v 0 1 1 0 1 ? 1.386 1.400 1.414 v 1 1 1 0 1 ? 1.411 1.425 1.439 v 0 1 1 0 0 ? 1.436 1.450 1.465 v 1 1 1 0 0 ? 1.460 1.475 1.490 v 0 1 0 1 1 ? 1.485 1.500 1.515 v 1 1 0 1 1 ? 1.510 1.525 1.540 v 0 1 0 1 0 ? 1.535 1.550 1.566 v 1 1 0 1 0 ? 1.559 1.575 1.591 v 0 1 0 0 1 ? 1.584 1.600 1.616 v 1 1 0 0 1 ? 1.609 1.625 1.641 v 0 1 0 0 0 ? 1.634 1.650 1.667 v 1 1 0 0 0 ? 1.658 1.675 1.692 v 0 0 1 1 1 ? 1.683 1.700 1.717 v 1 0 1 1 1 ? 1.708 1.725 1.742 v 0 0 1 1 0 ? 1.733 1.750 1.768 v 1 0 1 1 0 ? 1.757 1.775 1.793 v 0 0 1 0 1 ? 1.782 1.800 1.818 v 1 0 1 0 1 ? 1.807 1.825 1.843 v input threshold v id25 , v id3 , v id2 , v id1 , v id0 1.00 1.25 1.5 v input pull ? up resistance v id25 , v id3 , v id2 , v id1 , v id0 25 50 100 k pull ? up voltage ? 3.15 3.3 3.45 v
cs5308 http://onsemi.com 5 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v cch1 = v cch2 < 20 v; 4.5 v < v ccl =v ccl12 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k, c comp = 0.1 f, c ref = 0.1 f, dac code 01000 (1.65 v), c vcc = 0.1 f; unless otherwise specified.) characteristic unit max typ min test conditions power good output power good fault delay cs ref = dac to dac 15% 25 50 100 s pwrgd low voltage i pwrgd = 4.0 ma ? 250 400 mv output leakage current v pwrgd = 5.5 v ? 0.1 10 a lower threshold ? ? 15 ? 12 ? 9.0 % upper threshold ? 9.0 12 15 % voltage feedback error amplifier v fb bias current, (note 2.) 0.9 v < v fb < 1.9 v 9.4 10.3 11.1 a comp source current comp = 0.5 v to 2.0 v; v fb = 1.6 v 15 30 60 a comp sink current comp = 0.5 v to 2.0 v; v fb = 1.7 v 15 30 60 a comp discharge threshold voltage ? 0.20 0.27 0.34 v transconductance ? 10 a < i comp < +10 a ? 32 ? mmho output impedance ? ? 2.5 ? m open loop dc gain note 3. 60 90 ? db unity gain bandwidth 0.01 f ? 400 ? khz psrr @ 1.0 khz ? ? 70 ? db comp max voltage v fb = 1.6 v comp open 2.4 2.7 ? v comp min voltage v fb = 1.7 v comp open ? 0.1 0.2 v hiccup latch discharge current ? 2.0 5.0 10 a comp discharge ratio ? 4.0 6.0 10 ? pwm comparators minimum pulse width cs1 = cs2 = cs ref ? 350 475 ns channel startup offset v(cs1) = v(cs2) = v(v fb ) = v(cs ref ) = 0 v; measure v(comp) when gate(h)1,2 switch high 0.3 0.4 0.5 v vtt power good vtt threshold ? 1.03 1.05 1.07 v vtt pgd low voltage i vttpgd = 4.0 ma ? 0.25 0.4 v vtt pgd leakage current vtt pgd = 5.5 v ? 0.1 10 a vtt ct threshold voltage ? 1.0 1.05 1.10 v vtt ct charge current note 2. 15 30 45 a vtt ct discharge threshold ? 0.24 0.32 0.38 v gates high voltage (ac) measure v ccx ? gatex, note 3. ? 0 1.0 v low voltage (ac) measure gatex, note 3. ? 0 0.5 v rise time gatex 1.0 v < gate < 8.0 v; v ccx = 10 v ? 35 80 ns 2. the v fb bias current and vtt ct charge currents change with the value of r osc per figure 4. 3. guaranteed by design. not tested in production.
cs5308 http://onsemi.com 6 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v cch1 = v cch2 < 20 v; 4.5 v < v ccl =v ccl12 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k, c comp = 0.1 f, c ref = 0.1 f, dac code 01000 (1.65 v), c vcc = 0.1 f; unless otherwise specified.) characteristic unit max typ min test conditions gates fall time gatex 8.0 v > gate > 1.0 v; v ccx = 10 v ? 35 80 ns gate(h)x to gate(l)x delay gate(h)x < 2.0 v, gate(l)x > 2.0 v 30 65 110 ns gate(l)x to gate(h)x delay gate(l)x < 2.0 v, gate(h)x > 2.0 v 30 65 110 ns gate pull ? down force 100 a into gate with no power applied to v cchx and v cclx = 2.0 v ? 1.2 1.6 v oscillator switching frequency r osc = 32.4 k 340 400 460 khz switching frequency r osc = 63.4 k, note 4. 150 200 250 khz switching frequency r osc = 16.2 k, note 4. 600 800 1000 khz r osc voltage ? ? 1.0 ? v phase delay rising edge only 165 180 195 deg adaptive voltage positioning v drp offset cs1 = cs2 = cs ref , v fb = comp, measure v drp ? comp ? 15 ? 15 mv v drp operating voltage range measure v drp ? gnd, note 4. 0.1 ? 2.3 v maximum v drp voltage (cs1 = cs2) ? cs ref = 50 mv, v fb = comp measure v drp ? comp 260 320 400 mv current share amp to v drp gain ? 2.6 3.2 4.0 v/v current sensing and sharing cs1 ? cs2 input bias current v(cx) = v(cs ref ) = 0 v ? 0.1 2.0 a cs ref input bias current ? ? 0.5 2.0 a current sense amplifier gain ? 3.05 3.50 3.95 v/v current sense amp mismatch (the sum of gain and offset errors.) 0 < csx ? cs ref < 50 mv. note 4. ? 5.0 ? 5.0 mv current sense input to i lim gain i lim = 1.0 v 5.5 6.5 7.5 v/v current limit filter slew rate note 4. 7.5 15 40 mv/ s i lim operating voltage range note 4. 0.1 ? 1.3 v i lim bias current 0 v < i lim < 1.0 v ? 0.1 1.0 a single phase pulse by pulse current limit: v(cx) ? v(cs ref ) ? 90 105 135 mv current sense amplifier bandwidth note 4. 1.0 ? ? mhz 4. guaranteed by design. not tested in production.
cs5308 http://onsemi.com 7 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v cch1 = v cch2 < 20 v; 4.5 v < v ccl =v ccl12 < 14 v; c gate = 3.3 nf, r rosc = 32.4 k, c comp = 0.1 f, c ref = 0.1 f, dac code 01000 (1.65 v), c vcc = 0.1 f; unless otherwise specified.) characteristic unit max typ min test conditions general electrical specifications v ccl operating current v fb = comp (no switching) ? 20.5 26.0 ma v ccl12 operating current v fb = comp (no switching) ? 8.0 11 ma v cch1 operating current v fb = comp (no switching) ? 2.8 4.0 ma v cch2 operating current v fb = comp (no switching) ? 2.5 3.5 ma v ccl start threshold gates switching, comp charging 4.05 4.3 4.5 v v ccl stop threshold gates stop switching, comp discharging 3.75 4.1 4.35 v v ccl hysteresis gates not switching, comp not charging 100 200 300 mv v cch1 start threshold gates switching, comp charging 8.0 8.5 9.0 v v cch1 stop threshold gates stop switching, comp discharging 7.5 8.0 8.5 v v cch1 hysteresis gates not switching, comp not charging 300 500 700 mv reference output v ref output voltage 0 ma < i(v ref ) < 1.0 ma 3.2 3.3 3.4 v internal ramp ramp height @ 50% dtc cs1 = cs2 = cs ref ? 125 ? mv 5. guaranteed by design. not tested in production.
cs5308 http://onsemi.com 8 package pin description package pin # pin symbol function 28 lead so wide 1 comp output of the error amplifier and input for the pwm compara- tors. 2 v fb voltage feedback pin. to use adaptive voltage positioning, set the light load offset voltage by connecting a resistor be- tween v fb and v out . the resistor and the v fb bias current determine the offset. for no adaptive positioning connect v fb directly to v out . 3 v drp current sense output for adaptive voltage positioning (avp). the offset of this pin above the dac voltage is proportional to the output current. connect a resistor from this pin to v fb to set the amount of avp or leave this pin open for no avp. this pin?s maximum working voltage is 2.3 vdc. 4 ref reference output. decouple to lgnd with 0.1 f. 5 i lim sets threshold for current limit. connect to reference through a resistive divider. this pin?s maximum working voltage is 1.3 vdc. 6 ? 10 vid pins voltage id dac inputs. these pins are internally pulled up to 3.3 v if left open. 11 pwrgd power good output. open collector output goes low when cs ref is out of regulation. 12 cs ref reference for current sense amplifiers, input to the power good comparators, and fast feedback connection to the pwm comparator. connect this pin to the output voltage through a resistor equal to 1/5th the value of the current sense resistors. the input voltage to this pin must not ex- ceed the maximum vid (dac) setting by more than 100 mv. 13, 14 cs1 ? cs2 current sense inputs. connect current sense network for the corresponding phase to each input. the input voltages to these pins must be kept within 105 mv of cs ref or pulse ? by ? pulse current limit will be triggered. 15 vtt vtt sense input. the voltage on this pin must be higher than the vtt threshold (nominally 1.05 v) or switching will not occur. 16 vtt ct 1.0 ms timer for vtt power good. 17 vttp gd vtt power good output. open collector, pulls down when vtt < 1.03 v. 18 v cch2 power for channel 2 high side gate driver. 19, 20 gate(h)2, gate(l)2 high and low side gate drivers for channels 1 and 2. 21 v ccl12 power for both low side gate drivers. 22 pgnd return for all gate drivers. 23, 24 gate(l)1, gate(h)1 low and high side gate drivers for channels 1 and 2. 25 v cch1 power for channel 1 high side gate driver. 26 v ccl power for logic. uvlo sense for supply connects to this pin. 27 lgnd ground for internal control circuits and the ic substrate con- nection. 28 r osc a resistor from this pin to ground sets operating frequency.
cs5308 http://onsemi.com 9 + ? + ? ovic ? + start stop 8.5 v + ? 8.0 v ? + start stop 4.3 v + ? 4.1 v v ttpgd set dominant s r reset dominant s r fault + ? resc comp + ? 0.27 v + ? avpa 1.86 v ccl v cch1 v id25 mv v id0 v id1 v id2 v id3 3.3 v ref v ccl ramp 1 ? + pwm1 co1 dac out + ? maxc1 + ? 0.4 v reset dominant s r gate non ? overlap v cch1 v ccl1 pgnd ph1 i lim vtt pgd vtt ct set dominant s r v cc v ccl12 v cch1 i vttct 1.0 v ? + vtt + ? 1.05 v + ? 0.32 v + ? + ? dly 50 s pwrgd cs ref dac*1.12 dac*0.88 ? + csa1 + ? avpa dac 3.50 0.91 cs1 dac out fault 1 2 idchg osc ph1 ramp 1 current source gen ibias + ? ea dac out 12 fault v drp comp v fb r osc lgnd ref cs ref ? + csa2 cs2 co1 co2 vitotal ? 0.4 v + v cch2 reset dominant s r v cch2 v ccl2 ph2 gate non ? overlap gate(h)2 ramp 2 pwm2 co2 + ? maxc2 + ? 0.4 v ? + fault fault gate(l)2 gate(h)1 gate(l)2 ph2 ramp 2 figure 2. block diagram
cs5308 http://onsemi.com 10 typical performance characteristics figure 3. oscillator frequency vs. r osc figure 4. v fb & vtt ct currents vs. r osc value figure 5. gate(h) rise time vs. load capacitance measured from 4.0 v to 1.0 v with v cc at 5.0 v figure 6. gate(h) fall time vs. load capacitance measured from 4.0 v to 1.0 v with v cc at 5.0 v figure 7. gate(l) rise time vs. load capacitance measured from 1.0 v to 4.0 v with v cc at 5.0 v figure 8. gate(l) fall time vs. load capacitance measured from 1.0 v to 4.0 v with v cc at 5.0 v frequency (khz) 100 r osc value (k ) 300 400 500 600 700 800 900 200 10 20 30 40 50 60 70 0 time, ns 0 load capacitance, nf 20 60 80 100 120 2468 12 10 14 16 40 0 time, ns 0 load capacitance, nf 20 60 80 100 120 2468 12 10 14 16 40 0 time, ns 0 load capacitance, nf 20 60 80 100 120 2468 12 10 14 16 40 0 time, ns 0 load capacitance, nf 20 60 80 100 120 2468 12 10 14 16 40 10 v fb bias current ( a) ? 50 r osc resistance (k ) ? 45 ? 30 ? 25 ? 20 ? 15 ? 5 0 20 30 40 50 60 70 80 90 ? 10 ? 35 ? 40 5 15 45 55 65 75 95 105 85 35 25 vtt ct charge current ( a) i vfb @ 25 c i vttct @ 25 c
cs5308 http://onsemi.com 11 applications information overview the cs5308 dc/dc controller from on semiconductor was developed using the enhanced v 2 topology to meet requirements of low voltage, high current loads with fast transient requir ements. enhanced v 2 combines the original v 2 topology with peak current ? mode control for fast transient response and current sensing capability. the addition of an internal pwm ramp and implementation of fast ? feedback directly from v core has improved transient response and simplified design. the cs5308 includes vtt monitoring, vtt pgd , pwrgd, and mosfet gate drivers to provide a ?fully integrated solution? to simplify design, minimize circuit board area, and reduce overall system cost. two advantages of a multi ? phase converter over a single ? phase converter are current sharing and increased apparent output frequency. curre nt sharing allows the designer to use less inductance in each phase than would be required in a single ? phase converter. the smaller inductor will produce larger ripple currents but the total per phase power dissipation is reduced because the rms current is lower. transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. increased apparent output frequency is desirable because the off ? time and the ripple voltage of the two ? phase converter will be less than that of a single ? phase converter. fixed frequency multi ? phase control in a multi ? phase converter, multiple converters are connected in parallel and are switched on at different times. this reduces output current from the individual converters and increases the apparent ripple frequency. because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. the cs5308 controller uses two ? phase, fixed frequency, enhanced v 2 architecture to measure and control currents in individual phases. each phase is delayed 180 from the previous phase. normally, gate(h) transitions to a high voltage at the beginning of each oscillator cycle. inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the pwm comparator and bring gate(h) low. once gate(h) goes low, it will remain low until the beginning of the next oscillator cycle. while gate(h) is high, the enhanced v 2 loop will respond to line and load variations. on the other hand, once gate(h) is low, the loop can not respond until the beginning of the next pwm cycle. therefore, constant frequency enhanced v 2 will typically respond to disturbances within the off ? time of the converter. the enhanced v 2 architecture measures and adjusts the output current in each phase. an additional input (csn) for inductor current information has been added to the v 2 ? loop for each phase as shown in figure 9. the triangular inductor current is measured differentially across r s , amplified by csa and summed with the channel startup offset, the internal ramp, and the output voltage at the non ? inverting input of the pwm comparator. the purpose of the internal ramp is to compensate for propagation delays in the cs5308. this provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation, and pwm duty cycles above 50% without external slope compensation. as the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the pwm comparator rises and terminates the pwm cycle. if the inductor starts a cycle with higher current, the pwm cycle will terminate earlier providing negative feedback. the cs5308 provides a csn input for each phase, but the cs ref and comp inputs are common to all phases. current sharing is accomplished by referencing all phases to the same cs ref and comp pins, so that a phase with a lar ger current signal will turn off earlier than a phase with a smaller current signal.
cs5308 http://onsemi.com 12 figure 9. enhanced v 2 control employing resistive current sensing and additional internal ramp + swnode ln rln rsn csn csa con cs ref + v out (v core ) ?fast ? feedback? connection + pwm comp to f/f reset channel start ? up offset + e.a. dac out v fb comp internal ramp + n = 1 or 2 ? + enhanced v 2 responds to disturbances in v core by employing both ?slow? and ?fast? voltage regulation. the internal error amplifier performs the slow regulation. depending on the gain and frequency compensation set by the amplifier?s external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in 1 ? 2 pwm cycles. fast voltage feedback is implemented by a direct connection from v core to the non ? inverting pin of the pwm comparator via the summation with the inductor current, internal ramp, and offset. a rapid increase in load current will produce a negative offset at v core and at the output of the summer. this will cause the pwm duty cycle to increase almost instantly. fast feedback will typically adjust the pwm duty ? cycle in one pwm cycle. as shown in figure 9, a ?partial? internal ramp (nominally 125 mv at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the pwm comparator. this additional ramp compensates for propagation time delays from the current sense amplifier (csa), the pwm comparator, and the mosfet gate drivers. as a result, the minimum on time of the controller is reduced and lower duty cycles may be achieved at higher freque ncies. also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the r csn c csn (n = 1 or 2) time constant of the feedback components from v core to the csn pin. including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. when the average output current is zero, the comp pin will be: v comp v out @0a channel_startup_offset int_ramp g csa ext_ramp 2 int_ramp is the ?partial? internal ramp value at the corresponding duty cycle, ext_ramp is the peak ? to ? peak external steady ? state ramp at 0 a, g csa is the current sense amplifier gain (nominally 3.5 v/v), and the channel startup offset is typically 0.40 v. the magnitude of the ext_ramp can be calculated from: ext_ramp d (v in v out ) (r csn c csn f sw ) for example, if v out at 0 a is set to 1.745 v with avp and the input voltage is 5.0 v, the duty cycle (d) will be 1.745/5.0 or 35%. int_ramp will be 125 mv ? 35/50 = 87.5 mv. realistic values for r csn , c csn and f sw are 60 k , 0.01 f, and 300 khz using these ext_ramp will be 6.3 mv. v comp 1.745 v 0.40 v 87.5 mv 3.5 v v 6.3 mv 2 2.244 vdc. if the comp pin is held steady and the inductor current changes, there must also be a change in the output voltage. or, in a closed loop configuration when the output current changes, the comp pin must move to keep the same output voltage. the required change in the output voltage or comp pin depends on the scaling of the current feedback signal and is calculated as: v r s g csa i out . the single ? phase power stage output impedance is: single stage impedance v out i out r s g csa the multi ? phase power stage output impedance is the single ? phase output impedance divided by the number of phases. the output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the comp pin. the peak output current can be calculated from: i out,peak ( v co mp v ou t offset ) ( r s g cs a ) figure 10 shows the step response of the comp pin at a fixed level. before t1 the converter is in normal steady state
cs5308 http://onsemi.com 13 operation. the inductor current provides a portion of the pwm ramp through the current sense amplifier. the pwm cycle ends when the sum of the current ramp, the ?partial? internal ramp voltage signal and offset exceed the level of the comp pin. at t1 the output current increases and the output voltage sags. the next pwm cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the v fb pin and the cycle ends at t2. after t2 the output voltage remains lower than at light load and the average current signal level (csn output) is raised so that the sum of the current and voltage signal is the same as with the original load. in a closed loop system the comp pin would move higher to restore the output voltage to the original level. swnode v fb (v out ) internal ramp csa out w/ exaggerated delays comp ? offset csa out + ramp + cs ref t1 t2 figure 10. open loop operation figure 11. enhanced v 2 control employing lossless inductive current sensing and internal ramp + swnode ln r csn rln csn csa con cs ref + v out (v core ) ?fast ? feedback? connection + pwm comp to f/f reset channel start ? up offset + e.a. dac out v fb comp internal ramp + n = 1 or 2 c csn ? + inductive current sensing for lossless sensing, current can be sensed across the inductor as shown in figure 11. in the diagram, l is the output inductance and r l is the inherent inductor resistance. to compensate the current sense signal, the values of r csn and c csn are chosen so that l/r l = r csn ? c csn . if this criteria is met, the current sense signal will be the same shape as the inductor current and the voltage signal at csn will represent the instantaneous value of inductor current. also, the circuit can be analyzed as if a sense resistor of value r l was used as a sense resistor (r s ). when choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. copper magnet wire has a temperature coefficient of 0.39% per c. the increase in winding resistance at higher temperatures should be considered when setting the i lim threshold. if a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in figure 9. current sharing accuracy printed circuit board (pcb) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. for accurate current sharing, the current sense inputs should sense the current at relatively the same point for each phase and the connection to the cs ref pin should be made so that no phase is favored. in some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance. the total current sense resistance used for calculations must include any pcb trace resistance between the csn input and the cs ref input that carries inductor current.
cs5308 http://onsemi.com 14 current sense amplifier (csa) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. the worst case current sense amplifier input mismatch is 5.0 mv and will typically be within 3.0 mv. the difference in peak currents between phases will be the csa input mismatch divided by the current sense resistance. if all current sense components are of equal resistance a 3.0 mv mismatch with a 2.0 m sense resistance will produce a 1.5 a difference in current between phases. external ramp size and current sensing the internal ramp allows flexibility of current sense time constant. typically, the current sense r csn c csn time constant (n = 1 or 2) should be equal to or slower than the inductor?s time constant. if rc is chosen to be smaller (faster) than l/r l , the ac or transient portion of the current sensing signal will be scaled larger than the dc portion. this will provide a larger steady state ramp, but circuit performance will be affected and must be evaluated carefully. the current signal will overshoot during transients and settle at the rate determined by r csn ? c csn . it will eventually settle to the correct dc level, but the error will decay with the time constant of r csn ? c csn . if this error is excessive it will effect transient response, adaptive positioning and current limit. during a positive current transient, the comp pin will be required to overshoot in response to the current signal in order to maintain the output voltage. similarly, the v drp signal will overshoot which will produce too much transient droop in the output voltage. single phase overcurrent will trip earlier than it would if compensated correctly and hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents. the waveforms in figure 12 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of l = 500 nh, r l = 1.6 m , r csn = 20 k and c csn = 0.01 f. for ideal current signal compensation the value of r csn should be 31 k . due to the faster than ideal rc time constant there is an overshoot of 50% and the overshoot decays with a 200 s time constant. with this compensation the i lim pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step. figure 12. inductive sensing waveform during a load step with fast rc time constant (50 s/div) current limit two levels of over ? current protection are provided. first, if the voltage on the current sense pins (either cs1 or cs2) exceeds cs ref by more than a fixed threshold (single pulse current limit), the pwm comparator is turned off. this provides fast peak current protection for individual phases. second, the individual phase currents are summed and low ? pass filtered to compare an averaged current signal to a user adjustable voltage on the i lim pin. if the i lim voltage is exceeded, the fault latch trips and the soft start capacitor is discharged until the comp pin reaches 0.27 v. then soft start begins. the converter will continue to operate in a low current hiccup mode until the fault condition is corrected. overvoltage protection overvoltage protection (ovp) is provided as a result of the normal operation of the enhanced v 2 control topology with synchronous rectifiers. the control loop responds to an overvoltage condition within 400 ns, causing the top mosfet to shut off and the synchronous (lower) mosfet to turn on. this results in a ?crowbar? action to clamp the output voltage and prevent damage to the load. the regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. transient response and adaptive positioning for applications with fast transient currents the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. adaptive voltage positioning can reduce peak ? peak output voltage deviations during load transients and allow for a smaller output filter. the output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. for low
cs5308 http://onsemi.com 15 current applications a droop resistor can provide fast accurate adaptive positioning. however, at high currents the loss in a droop resistor becomes excessive. for example; in a 50 a converter a 1 m resistor to provide a 50 mv change in output voltage between no load and full load would dissipate 2.5 watts. lossless adaptive positioning is an alternative to using a droop resistor, but must respond to changes in load current. figure 13 shows how adaptive positioning works. the waveform labeled normal shows a converter without adaptive positioning. on the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. with fast (ideal) adaptive positioning the peak to peak excursions are cut in half. in the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. adaptive positioning adaptive positioning normal fast slow limits figure 13. adaptive positioning the controller can be configured to adjust the output voltage based on the output current of the converter. (refer to the application diagram in figure 1.) to set the no ? load positioning, a resistor is placed between the output voltage and v fb pin. the v fb bias current will develop a voltage across the resistor to adjust the no ? load output voltage. the v fb bias current is dependent on the value of r osc as shown in the data sheets. during no ? load conditions the v drp pin is at the same voltage as the v fb pin, so none of the v fb bias current flows through the v drp resistor. when output current increases the v drp pin increases proportionally and the v drp pin current offsets the v fb bias current and causes the output voltage to decrease. the response during the first few microseconds of a load transient are controlled prim arily by power stage output impedance and the esr and esl of the output filter. the transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. if the current signal is too large or the error amp too slow there will be a long transition to the final voltage after a transient. this will be most apparent with lower capacitance output filters. error amp compensation & tuning the transconductance error amplifier requires a capacitor (c cmp2 in the applications diagram) between the comp pin and gnd for two reasons. first, this capacitor stabilizes the transconductance error amplifier. values less than a few nf may cause oscillations of the comp voltage. these oscillations will increase the output voltage jitter. second, this capacitor sets the soft start time when power is applied to the converter or the converter is enabled. the internal error amplifier will source approximately 30 a during soft start and no switching will occur until the comp voltage exceeds the channel startup offset (nominally 0.4 v). the comp voltage will ramp up to the value shown previously (repeated here for convenience): v comp v out @0a channel_startup_offset int_ramp g csa ext_ramp 2 the rc network between the comp pin and the soft start capacitor (r cmp1 and c cmp1 ) allows the comp voltage to slew quickly during transient loading of the converter. without this network the error amplifier would have to drive the large soft start/stability ca pacitor directly, which would drastically limit the slew ra te of the comp voltage. the r cmp1 /c cmp1 network allows the comp voltage to undergo a step change in voltage of approximately r cmp1 ? i comp . the capacitor (c amp ) between the comp pin and the inverting error amplifier input (the v fb pin) and the parallel combination of the resistors r fbk1 and r drp1 determine the bandwidth of the error amplifier. the gain of the error amplifier crosses 0 db at a high enough frequency to give a quick transient response, but well below the switching frequency to minimize ripple and noise on the comp pin. a capacitor in parallel with the v fb resistor (c fbk2 ) adds a zero to boost phase near the crossover frequency to improve loop stability. setting ? up and tuning the error amplifier is a three step process. first, the no ? load and full ? load adaptive voltage positioning (avp) are set using r fbk1 and r drp1 , respectively. second, the current sense time constant and error amplifier gain are adjusted with r csn and c amp while monitoring v out during transient loading. lastly, the peak ? to ? peak voltage ripple on the comp pin is examined when the converter is fully loaded to insure low output voltage jitter. the details of this process are covered in the design procedure section. undervoltage lockout (uvlo) the controller has undervoltage lockout functions connected to two pins. one, intended for the logic and low ? side drivers, with approximately a 4.2 v turn ? on threshold is connected to the v cc pin. a second, for the high side drivers, with approximately an 8.25 v threshold, is connected to the v cch pin. the uvlo threshold for the high side drivers varies with the part type. in many applications this function will be disabled or will only check that the applicable supply is on ? not that is at a high enough voltage to run the converter. see individual data sheets for more information on uvlo.
cs5308 http://onsemi.com 16 soft start enable, and hiccup mode a capacitor between the comp pin and gnd controls soft start and hiccup mode slopes. a 0.1 f capacitor with the 30 a charge current will allow the output to ramp up at 0.3 v/ms or 1.5 v in 5 ms at start ? up. when a fault is detected due to an overcurrent condition the converter will enter a low duty cycle hiccup mode. during hiccup mode the converter will not switch from the time a fault is detected until the soft start capacitor has discharged below the soft start discharge threshold and then charged back up above the channel start up offset. the comp pin will disable the converter when pulled below 0.27 v vtt monitoring & vtt power good (vtt pgd ) the cs5308 includes vtt monitoring, delay timing and an open ? collector vtt power good (vtt pgd ) output. a comparator with a threshold of approximately 1.05 v monitors vtt. at power ? up, vtt pgd is held low and is released a short time after vtt crosses the 1.05 v threshold. the time between vtt stabilizing and the release of vtt pgd is set by a capacitor (c vtt ) at the open ? collector vtt ct pin. the voltage at the vtt ct pin will ramp from its v ce(sat) voltage, approximately 0.25 v, to 1 v before vtt pgd is pulled high. the vtt ct charging current and c vtt set the vtt pgd delay time. the delay time can be calculated using: t d,vtt (1 v 0.25 v) c vtt vtt ct _current. the vtt ct charging current is dependent on the selection of the oscillator frequency. see figure 3 for a representation of oscillator frequency and charging current versus r osc value. if either vtt or vtt pgd are held low , the internal fault latch will be set, the controller will stop switching, and v core will be zero. power good (pwrgd) the open ? collector power good (pwrgd) pin is driven by a ?window ? comparator? monitoring v core . this comparator will transition high if v core is within 12% of the nominal vid setting. after a 50 s delay, the comparators output will saturate the open ? collector output transistor and the pwrgd pin will be pulled low. layout guidelines with the fast rise, high output currents of microprocessor applications, parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. typically, a multi ? layer board with at least one ground plane is recommended. if the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to route the currents away from the controller. the slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. additional power and ground planes or islands can be added as required for a particular layout. gate drives experience high di/dt during switching and the inductance of gate drive traces should be minimized. gate drive traces should be kept as short and wide as practical and should have a return path directly below the gate trace. output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. if required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. the current sense signals are typically tens of milli ? volts. noise pick ? up should be avoided wherever possible. current feedback traces should be routed away from noisy areas such as the switch node and gate drive signals. if the current signals are taken from a location other than directly at the inductor any additional resistance between the pick ? off point and the inductor appears as part of the inherent inductor resistances and should be considered in design calculations. the capacitors for the current feedback networks should be placed as close to the current sense pins as practical. after placing the cs5308 control ic, follow these guidelines to optimize the layout and routing: 1. place the 1 f power ? supply bypass (ceramic) capacitors close to their associated pins: v ccl , v cch1 , v cch2 , v ccl12 . 2. place the mosfets to minimize the length of the gate traces. orient the mosfets such that the drain connections are away from the controller and the gate connections are closest to the controller. 3. place the components associated with the internal error amplifier (r fbk1 , c fbk2 , c amp , r cmp1 , c cmp1 , c cmp2 , r drp1 ) to minimize the trace lengths to the pins v fb , v drp and comp. 4. place the current sense components (r cs1 , r cs2 , c cs1 , c cs2 , r csref , c csref ) near the cs1, cs2, and cs ref pins. 5. place the frequency setting resistor (r osc ) close to the r osc pin. the r osc pin is very sensitive to noise. route noisy traces, such as the swnodes and gate traces, away from the r osc pin and resistor. 6. place the vtt timing capacitor (c vtt ) and pull ? up resistor (r vtt ) near the vtt ct and vtt pgd pins. 7. place the mosfets and output inductors to reduce the size of the noisy swnodes. there is a trade ? off between reducing the size of the swnodes for noise reduction and providing adequate heat ? sinking for the synchronous mosfets. 8. place the input inductor and input capacitor(s) near the drain of the control (upper) mosfets. there is a trade ? off between reducing the size of this node to save board area and providing adequate heat ? sinking for the control mosfets.
cs5308 http://onsemi.com 17 9. place the output capacitors (electrolytic and ceramic) close to the processor socket or output connector. 10. the trace from the swnodes to the current sense components will be very noisy. route this away from more sensitive, low ? level traces. the ground layer can be used to help isolate this trace. 11. the gate traces are very noisy. route these away from more sensitive, low ? level traces. keep each gate signal on one layer and insure that there is an uninterrupted return path directly below the gate trace. the ground layer can be used to help isolate these traces. 12. don?t ?daisy chain? connections to ground from one via. allow each connection to ground to have its own via as close to the component as possible. 13. use a slot in the ground plane from the bulk output capacitors back to the input power connector to prevent high currents from flowing beneath the control ic. this slot should extend length ? wise under the control ic and separate the connections to ?signal ground? and ?power ground.? examples of signal ground include the capacitors at comp, cs ref , ref, and vtt ct , the resistors at r osc and i lim , and the lgnd pin to the controller. examples of power ground include the capacitors to v cch1 , v cch2 and v ccl12 , the source of the synchronous mosfets, and the pgnd pin to the controller. 14. the cs ref sense point should be equidistant between the output inductors to equalize the pcb resistance added to the current sense paths. this will insure acceptable current sharing. also, route the cs ref connection away from noisy traces such as the swnodes and gate traces. if noise from the swnodes or gate signals capacitively couples to the cs ref trace the external ramps will be very noise and voltage jitter will result. 15. ideally, the swnodes are exactly the same shape and the current sense points (connections to r cs1 and r cs2 ) are made at identical locations to equalize the pcb resistance added to the current sense paths. this will help to insure acceptable current sharing. 16. place the 0.1 f ceramic capacitors, c q1 and c q2 , close to the drains of the mosfets q1 and q2, respectively. design procedure 1. output capacitor selection the output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. typically, microprocessor applications will require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. the bulk capacitors provide ?hold up? during transient loading. the low impedance capacitors reduce steady ? state ripple and bypass the bulk capacitance when the output current changes very quickly. the microprocessor manufacturers usually specify a minimum number of ceramic capacitors. the designer must determine the number of bulk capacitors. choose the number of bulk output capacitors to meet the peak transient requirements. the formula below can be used to provide a starting point for the minimum number of bulk capacitors (n out,min ): n out,min esr per capacitor i o,max v o,max (1) in reality, both the esr and esl of the bulk capacitors determine the voltage change during a load transient according to: v o , max ( i o , max t) esl i o , max esr (2) unfortunately, capacitor manufacturers do not specify the esl of their components and the inductance added by the pcb traces is highly dependent on the layout and routing. therefore, it is necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors. 2. output inductor selection the output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady ? state and transient performance of the converter. when selecting an inductor the designer must consider factors such as dc current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size, and cost (usually the primary concern). in general, the output inductance value should be as low and physically small as possible to provide the best transient response and minimum cost. if a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. on the other hand, too low an inductance value will result in very large ripple currents in the power components (mosfets, capacitors, etc.) resulting in increased dissipation and lower converter efficiency. also, increased ripple currents will force the designer to use higher rated mosfets, oversize the thermal solution, and use more, higher rated input and output capacitors ? the converter cost will be adversely effected. one method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. lower ripple currents will result in less core and mosfet losses and higher converter efficiency. equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current ( ) per phase. the inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. conversely,
cs5308 http://onsemi.com 18 higher inductor values will result in less than the maximum ripple current. lo min (v in v out ) v out ( i o,max v in f sw ) (3) is the ripple current as a percentage of the maximum output current per phase ( = 0.15 for 15%, = 0.25 for 25%, etc.). if the minimum inductor value is used, the inductor current will swing % about its value at the center (1/2 the dc output current for a two ? phase converter). therefore, for a two ? phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + ) ? i o,max /2. the maximum inductor value is limited by the transient response of the converter. if the converter is to have a fast transient response then the inductor should be made as small as possible. if the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required, and the converter cost will be increased. for a given inductor value, its interesting to determine the times required to increase or decrease the current. for increasing current: t inc lo i o (v in v out ) (3.1) for decreasing current: t dec lo i o (v out ) (3.2) for typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. it may be more difficult for the converter to stay within the regulation limits when the load is removed than when it is applied ? excessive overshoot may result. the output voltage ripple can be calculated using the output inductor value derived in this section (lo min ), the number of output capacitors (n out,min ) and the per capacitor esr determined in the previous section: v out,p ? p (esr per cap n out,min ) (v in #phases v out ) d (lo min f sw ) (4) this formula assumes steady ? state conditions with no more than one phase on at any time. the second term in equation 4 is the total ripple current seen by the output capacitors. the total output ripple current is the ?time summation? of the two individual phase currents that are 180 degrees out ? of ? phase. as the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. therefore, the total output ripple current and voltage are reduced in a multi ? phase converter. 3. input capacitor selection the choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. the designer must choose capacitors that will support the worst case input voltage with adequate margin. to calculate the number of input capacitors one must first determine the total rms input ripple current. to this end, begin by calculating the average input current to the converter: i in,avg i o,max d (5) where: d is the duty cycle of the converter, d = v out /v in ; is the specified minimum efficiency; i o,max is the maximum converter output current. the input capacitors will discharge when the control fet is on and charge when the control fet is off as shown in figure 14. i c,max i c,min 0 a ? i in,avg fet on, caps discharging fet off, caps charging t on t/2 i c,in = i c,max ? i c,min figure 14. input capacitor current for a two ? phase converter the following equations will determine the maximum and minimum currents delivered by the input capacitors: i c,max i lo,max i in,avg (6) i c,min i lo,min i in,avg (7) i lo,max is the maximum output inductor current: i lo,max i o,max 2 i lo 2 (8) i lo,min is the minimum output inductor current: i lo,min i o,max 2 i lo 2 (9) i lo is the peak ? to ? peak ripple current in the output inductor of value lo: i lo (v in v out ) d (lo f sw ) (10) for the two ? phase converter, the input capacitor(s) rms current is then: i cin,rms [2d (i c,min 2 i c,min i c,in i c , in 2 3) i in , avg 2 (1 2d)] 1 2 (11) select the number of input capacitors (n in ) to provide the rms input current (i cin,rms ) based on the rms ripple current rating per capacitor (i rms,rated ): n in i cin,rms i rms,rated (12)
cs5308 http://onsemi.com 19 for a two ? phase converter with perfect efficiency ( = 1), the worst case input ripple ? current will occur when the converter is operating at a 25% duty cycle. at this operating point, the parallel combination of input capacitors must support an rms ripple current equal to 25% of the converter?s dc output current. at other duty cycles, the ripple ? current will be less. for example, at a duty cycle of either 10% or 40%, the two ? phase input ripple ? current will be approximately 20% of the converter?s dc output current. in general, capacitor manufacturers require derating to the specified ripple ? current based on the ambient temperature. more capacitors will be required because of the current derating. the designer should be cognizant of the esr of the input capacitors. the input capacitor power loss can be calculated from: p cin i cin,rms 2 esr_per_capacitor n in (13) low esr capacitors are recommended to minimize losses and reduce capacitor heating. the life of an electrolytic capacitor is reduced 50% for every 10 c rise in the capacitor?s temperature. 4. input inductor selection the use of an inductor between the input capacitors and the power source will accomplish two objectives. first, it will isolate the voltage source and the system from the noise generated in the switching supply. second, it will limit the inrush current into the input capacitors at power up. large inrush currents will reduce the expected life of the input capacitors. the inductor?s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. + + vi 5.0 v li tbd ci 2 6sp680 esr ci 13 m/2 = 6.5 m q2 q1 lo 825 nh esr co 23 m/5 = 4.6 m 14 u(t) co 5 6.3za1000m10x16 vi(t = 0) = 5.0 v swnode vo(t = 0) = 1.745 v v ci i lo v out i li max di/dt occurs in first few pwm cycles. figure 15. calculating the input inductance + ? the worst case input current slew rate will occur during the first few pwm cycles immediately after a step ? load change is applied as shown in figure 15. when the load is applied, the output voltage is pulled down very quickly. current through the output inductors will not change instantaneously so the initial transient load current must be conducted by the output capacitors. the output voltage will step downward depending on the magnitude of the output current (i o,max ), the per capacitor esr of the output capacitors (esr out ), and the number of the output capacitors (n out ) as shown in figure . assuming the load current is shared equally between the two phases, the output voltage at full, transient load will be: v out,full ? load (14) v out,no ? load (i o,max 2) esr out n out when the control mosfet (q1 in figure 15) turns on, the input voltage will be applied to the opposite terminal of the output inductor (the swnode). at that instant, the voltage across the output inductor can be calculated as: v lo v in v out,full ? load (15) v in v out,no ? load (i o,max 2) esr out n out the differential voltage across the output inductor will cause its current to increase linearly with time. the slew rate of this current can be calculated from: di lo dt v lo lo (16) current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. the amount of voltage drop across the input capacitors ( v ci ) is determined by the number of input capacitors (n in ), their per capacitor esr (esr in ), and the current in the output inductor according to:
cs5308 http://onsemi.com 20 v ci esr in n in di lo dt t on esr in n in di lo dt d f sw (17) before the load is applied, the voltage across the input inductor (v li ) is very small ? the input capacitors charge to the input voltage, v in . after the load is applied the voltage drop across the input capacitors, v ci , appears across the input inductor as well. knowing this, the minimum value of the input inductor can be calculated from: li min v li di in dt max v ci di in dt max (18) di in /dt max is the maximum allowable input current slew rate (specified as 0.1 a/ s or 0.1 10 6 a/s for vrm 8.5). the input inductance value calculated from equation 18 is relatively conservative. it assumes the supply voltage is very ?stiff? and does not account for any parasitic elements that will limit di/dt such as stray inductance. also, the esr values of the capacitors specified by the manufacturer?s data sheets are worst case high limits. in reality input voltage ?sag,? lower capacitor esrs, and stray inductance will help reduce the slew rate of the input current. as with the output inductor, the input inductor must support the maximum current without saturating the magnetic. also, for an inexpensive iron powder core, such as the ? 26 or ? 52 from micrometals, the inductance ?swing? with dc bias must be taken into account ? inductance will decrease as the dc in put current increases. at the maximum input current, the inductance must not decrease below the minimum value or the di/dt will be higher than expected. 5. mosfet & heatsink selection power dissipation, package size, and thermal solution drive mosfet selection. to adequately size the heat sink, the design must first predict the mosfet power dissipation. once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the control or upper mosfet will display both switching and conduction losses. the synchronous or lower mosfet will exhibit only conduction losses because it switches into nearly zero voltage. however, the body diode in the synchronous mosfet will suffer diode losses during the non ? overlap time of the gate drivers. for the upper or control mosfet, the power dissipation can be approximated from: p d,control (i rms,cntl 2 r ds(on) ) (i lo,max q switch i g v in f sw ) (q oss 2 v in f sw ) (v in q rr f sw ) (19) the first term represents the conduction or ir losses when the mosfet is on while the second term represents the switching losses. the third term is the losses associated with the control and synchronous mosfet output charge when the control mosfet turns on. the output losses are caused by both the control and synchronous mosfet but are dissipated only in the control fet. the fourth term is the loss due to the reverse recovery time of the body diode in the synchronous mosfet. the first two terms are usually adequate to predict the majority of the losses. where i rms,cntl is the rms value of the trapezoidal current in the control mosfet: (20) i rms,cntl d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 i lo,max is the maximum output inductor current: i lo,max i o,max 2 i lo 2 (21) i lo,min is the minimum output inductor current: i lo,min i o,max 2 i lo 2 (22) i o,max is the maximum converter output current. d is the duty cycle of the converter: d v out v in (23) i lo is the peak ? to ? peak ripple current in the output inductor of value l o : i lo (v in v out ) d (lo f sw ) (24) r ds(on) is the on resistance of the mosfet at the applied gate drive voltage. q switch is the post gate threshold portion of the gate ? to ? source charge plus the gate ? to ? drain charge. this may be specified in the data sheet or approximated from the gate ? charge curve as shown in the figure 16. q switch q gs2 q gd (25) i d v gate v drain q gd q gs2 q gs1 v gs_th figure 16. mosfet switching characteristics i g is the output current from the gate driver ic. v in is the input voltage to the converter. f sw is the switching frequency of the converter.
cs5308 http://onsemi.com 21 q g is the mosfet total gate charge to obtain r ds(on) . commonly specified in the data sheet. v g is the gate drive voltage. q rr is the reverse recovery charge of the lower mosfet. q oss is the mosfet output charge specified in the data sheet. for the lower or synchronous mosfet, the power dissipation can be approximated from: p d,synch (i rms,synch 2 r ds(on) ) (vf diode i o,max 2 t_nonoverlap f sw ) (26) the first term represents the conduction or ir losses when the mosfet is on and the second term represents the diode losses that occur during the gate non ? overlap time. all terms were defined in the previous discussion for the control mosfet with the exception of: (27) i rms,synch 1 d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 where: vf diode is the forward voltage of the mosfet?s intrinsic diode at the converter output current. t_nonoverlap is the non ? overlap time between the upper and lower gate drivers to prevent cross conduction. this time is usually specified in the data sheet for the control ic. ? + + ?
r cs1 cs1 c cs1 l1 0 a g vdrp + ? r cs2 cs2 c cs2 l2 0 a g vdrp cs ref comp error amp vid setting ibias vfb r drp r vfbk v drp = vid v fb = vid v core i drp = 0 i fbk = ibias vfb v core = vid + ibias vfb r vfbk figure 17. avp circuitry at no ? load + ? when the mosfet power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature t (t j t a ) p d (28) where: t is the total thermal impedance ( jc + sa ); jc is the junction ? to ? case thermal impedance of the mosfet; sa is the sink ? to ? ambient thermal impedance of the heatsink assuming direct mounting of the mosfet (no thermal ?pad? is used); t j is the specified maximum allowed junction temperature; t a is the worst case ambient operating temperature. for to ? 220 and to ? 263 packages, standard fr ? 4 copper clad circuit boards will have approximate thermal resistances ( sa ) as shown below: pad size (in 2 /mm 2 ) single ? sided 1 oz. copper 0.50/323 60 ? 65 c/w 0.75/484 55 ? 60 c/w 1.00/645 50 ? 55 c/w 1.50/968 45 ? 50 c/w as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case mosfet r ds(on) ). also, the inductors and capacitors share the mosfet?s heatsinks and will add heat and raise the temperature of the circuit board and mosfet. for any new design, its advisable to have as
cs5308 http://onsemi.com 22 much heatsink area as possible ? all too often new designs are found to be too hot and require re ? design to add heatsinking. 6. adaptive voltage positioning there are two resistors that determine the adaptive voltage positioning: r vfbk and r drp . r vfbk establishes the no ? load ?high? voltage position and r drp determines the full ? load ?droop? voltage. resistor r vfbk is connected between v core and the v fb pin of the controller. at no load, this resistor will conduct the internal bias current of the v fb pin and develop a voltage drop from v core to the v fb pin. because the error amplifier regulates v fb to the dac setting, the output voltage, v core , will be higher by the amount ibias vfb ? r vfbk . this condition is shown in figure 17. to calculate r vfbk the designer must specify the no ? load voltage increase above the vid setting ( v no ? load ) and determine the v fb bias current. usually, the no ? load voltage increase is specified in the design guide for the processor that is available from the manufacturer. the v fb bias current is determined by the value of the resistor from r osc to ground (see figure in the data sheet for a graph of ibias vfb versus r_osc). the value of r vfbk can then be calculated: r vfbk v no ? load ibias vfb (29) resistor r drp is connected between the v drp and the v fb pins. at no ? load, the v drp and the v fb pins will both be at the dac voltage so this resistor will conduct zero current. however, at full ? load, the voltage at the v drp pin will increase proportional to the output inductor?s current while v fb will still be regulated to the dac voltage. current will be conducted from v drp to v fb by r drp . this current will be large enough to supply the v fb bias current and cause a voltage drop from v fb to v core across r fbk ? the converter?s output voltage will be reduced. this condition is shown in figure 18. ? + + ?
r cs1 cs1 c cs1 l1 i max /2 g vdrp + ? r cs2 cs2 c cs2 l2 i max /2 g vdrp cs ref comp error amp vid setting ibias vfb r drp r vfbk v drp = vid + i max ? r l ? g vdrp v fb = vid v core i drp i fbk v core = vid ? (i drp ? ibias vfb ) r vfbk figure 18. avp circuitry at full ? load i drp = i max ? r l ? g vdrp /r drp i fbk = i drp ? ibias vfb = vid ? i max r l g vdrp r fbk /r drp + ibias vfb r fbk + ? to determine the value of r drp the designer must specify the full ? load voltage reduction from the vid (dac) setting ( v out,full ? load ) and predict the voltage increase at the v drp pin at full ? load. usually, the full ? load voltage reduction is specified in the design guide for the processor that is available from the manufacturer. to predict the voltage increase at the v drp pin at full ? load ( v drp ), the designer must consider the output inductor?s resistance (r l ), the pcb trace resistance between the current sense points (r pcb ), and the controller ic?s gain from the current sense to the v drp pin (g vdrp ): v drp i o,max (r l r pcb ) g vdrp (30) the value of r drp can then be calculated: r drp v drp (ibias vfb v out,full ? load r vfbk ) (31) v out,full ? load is the full ? load voltage reduction from the vid (dac) setting. vout,full ? load is not the voltage change from the no ? load avp setting. 7. current sensing for inductive current sensing, choose the current sense network (r csn , c csn , n = 1 or 2) to satisfy r csn c csn lo (r l r pcb ) (32) for resistive current sensing, choose the current sense network (r csn , c csn , n = 1 or 2) to satisfy r csn c csn lo (r sense ) (33) this will provide an adequate starting point for r csn and c csn . after the converter is constructed, the value of r csn (and/or c csn ) should be fine ? tuned in the lab by observing the v drp signal during a step change in load current. tune
cs5308 http://onsemi.com 23 the r csn ? c csn network to provide a ?square ? wave? at the v drp output pin with maximum rise time and minimal overshoot as shown in figure 21. figure 19. v drp tuning waveforms. the rc time constant of the current sense network is too long (slow): v drp and v out respond too slowly. figure 20. v drp tuning waveforms. the rc time constant of the current sense network is too short (fast): v drp and v out both overshoot. figure 21. v drp tuning waveforms. the rc time constant of the current sense network is optimal: v drp and v out respond to the load current quickly without overshooting. 8. error amplifier tuning after the steady ? state (static) avp has been set and the current sense network has been optimized the error amplifier must be tuned. basically, the gain of the error amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the error amplifier?s feedback capacitor (c amp in the applications diagram). the bandwidth of the control loop will vary directly with the gain of the error amplifier. figure 22. the value of c amp is too high and the loop gain/bandwidth too low. comp slews too slowly which results in overshoot in v out . if c amp is too large the loop gain/bandwidth will be low, the comp pin will slew too slowly, and the output voltage will overshoot as shown in figure 22. on the other hand, if
cs5308 http://onsemi.com 24 c amp is too small the loop gain/bandwidth will be high, the comp pin will slew very quickly and overshoot. integrator ?wind up? is the cause of the overshoot. in this case the output voltage will transition more slowly because comp spikes upward as shown in figure 23. too much loop gain/bandwidth increase the risk of instability. in general, one should use the lowest loop gain/bandwidth as possible to achieve acceptable transient response ? this will insure good stability. if c amp is optimal the comp pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in figure 24. figure 23. the value of c amp is too low and the loop gain/bandwidth too high. comp moves too quickly, which is evident from the small spike in its voltage when the load is applied or removed. the output voltage transitions more slowly because of the comp spike. figure 24. the value of c amp is optimal. comp slews quickly without spiking or ringing. v out does not overshoot and monotonically settles to its final value. after the control loop is tuned to provide an acceptable transient response the steady ? state voltage ripple on the comp pin should be examined. when the converter is operating at full, steady ? state load, the peak ? to ? peak voltage ripple on the comp pin should be less than 20 mv pp as shown in figure 25. less than 10 mv pp is ideal. excessive ripple on the comp pin will contribute to output voltage jitter. figure 25. at full ? load (28 a) the peak ? to ? peak voltage ripple on the comp pin should be less than 20 mv for a well ? tuned/stable controller. higher comp voltage ripple will contribute to output voltage jitter. 9. current limit setting when the output of the current sense amplifier (co1 or co2 in the block diagram) exceeds the voltage on the i lim pin the part will enter hiccup mode. for inductive sensing, the i lim pin voltage should be set based on the inductor?s maximum resistance (r lmax ). the design must consider the inductor?s resistance increase due to current heating and ambient temperature rise. also, depending on the current sense points, the circuit board may add additional resistance. in general, the temperature coefficient of copper is +0.39% per c. if using a current sense resistor (r sense ), the i lim pin voltage should be set based on the maximum value of the sense resistor. to set the level of the i lim pin: v ilim (i out,lim i lo 2) r g ilim (34) where: i out,lim is the current limit threshold of the converter; i lo /2 is half the inductor ripple current; r is either (r lmax + r pcb ) or r sense; g ilim is the current sense to i lim gain. for the overcurrent protection to work properly, the current sense time constant (rc) should be slightly larger than the r l time constant. if the rc time constant is too fast, during step load changes the sensed current waveform will appear larger than the actual inductor current and will probably trip the current limit at a lower level than expected. 10. pwm comparator input voltage the voltage at the positive input terminal of the pwm comparator (see figure 9 or 11) is limited by the internal voltage supply of the controller (3.3 v), the size of the internal ramp, and the magnitude of the channel startup offset voltage. to prevent the pwm comparator from
cs5308 http://onsemi.com 25 saturating, the dif ferential input voltage from cs ref to csn (n = 1 or 2) must satisfy the following equation: v csref,max v con,max 310 mv d 2.45 v (35) where: v csref,max max vid setting w avp @ full load v con,max [v csn v csref ] g csa,max (i o,max 2 i lo 2) r max g csa,max r max r sense or (r l,max r pcb,max ) 11. vtt pgd delay time setting the vtt pgd signal is pulled low a predetermined delay time (t d,vtt ) after the vtt voltage crosses the vtt threshold. the vtt ct charge current and the capacitor value from the vtt ct pin to ground (c vtt ) determine the t d,vtt delay time. however, the choice of oscillator frequency and the value of r osc set the vtt ct charge current as shown in figure 4. therefore, delay time is simply set by the value of c vtt according to the following equation: t d,vtt (1 v 0.25v) c vtt vtt ct _current (36) 12. soft start time the soft start time (t ss ) can be calculated from: t ss (v comp r cmp1 i comp ) c cmp2 i comp (37) where: v comp v out @0a channel_startup_offset int_ramp g csa ext_ramp 2 i comp is the comp source current from the data sheet.
cs5308 http://onsemi.com 26 design example typical design requirements: v in = 5.0 vdc v out = 1.70 vdc (nominal) v out,ripple = 10 mv pp max vid range: 1.050 vdc ? 1.825 vdc i o,max = 28 a at full ? load i out,lim = 33 a min at 50 c (shutdown threshold) di in /dt = 0.1 a/ s max f sw = 335 khz = 81% minimum t a,max = 60 c t j,max = 115 c t d,vtt = 2.5 ms (vtt pgd delay time) t ss = 6.5 ms (soft start time) v out at no ? load (static) = +45 mv from vid setting = 1.745 vdc v out at full ? load (static) = ? 45 mv from vid setting = 1.655 vdc v out at full ? load (transient) = 90 mv from vid setting = 1.610 vdc 1. output capacitor selection first, choose a low ? cost, low ? esr output capacitor such as the rubycon 6.3za1000m10x16: 6.3 v, 1000 f, 1.65 a rms , 24 m , 10 16 mm. calculate the minimum number of output capacitors: n out,min esr per capacitor i o,max v o,max 24 m 28 a (1.745 v 1.610 v) 4.987 or 5 capacitors minimum (5000 f) (1) 2. output inductor selection calculate the minimum output inductance at i o,max according to equation 3 with 20% inductor ripple current ( = 0.20): lo min (v in v out ) v out ( i o,max v in f sw ) (5 v 1.655 v) 1.655 v (0.2 28 a 5v 335 khz) 590 nh (3) to save cost, we choose the inexpensive t50 52 core from micrometals: 33 nh/n 2 , 3.19 cm./turn. at 14 a per phase the permeability of this core will be approximately 80% of the permeability at 0 a. therefore, at 0 a we must achieve at least 590 nh/0.8 or 738 nh. using four turns results in only 528 nh, so we must use five turns of #16awg bifilar (2 m /ft.) to produce 825 nh. this inductor is available as part number ctx22 ? 15401 from coiltronics. use equation 4 to insure the output voltage ripple will satisfy the design goal with the minimum number of capacitors and the nominal output inductance: v out,p ? p (esr per cap n out,min ) (v in #phases v out ) d (lo min f sw ) (4) (24 m 5) (5.0 v 2 1.7 v) (1.7 v 5.0 v) (825 nh 335 khz) (4.8 m ) { 1.97 a } 9.45 mv the output voltage ripple will be decreased when output capacitors are added to satisfy transient loading requirements. we will need the nominal and worst case inductor resistances for subsequent calculations: r l 5 turns 3.19 cm turn 0.03218 ft cm 2m ft 1.03 m the inductor resistance will be maximized when the inductor is ?hot? due to the load current and the ambient temperature is high. assuming a 40 c temperature rise of the inductor at full ? load and a 25 c ambient temperature rise we can calculate: r l,max 1.03 m [1 0.39% c (40 c 25 c)] 1.29 m 3. input capacitor selection use equation 5 to determine the average input current to the converter: i in,avg i o,max d 28 a (1.655 v 5.0 v) 0.81 11.44 a (5) next, use equations 6 to 10: i lo (v in v out ) d (lo f sw ) (5 v 1.655 v) (1.655 v 5.0 v) (825 nh 335 khz) 4.00 app (10) i lo,max i o,max 2 i lo 2 28 a 2 4app 2 16 a (8) i lo,min i o,max 2 i lo 2 28 a 2 4app 2 12 a (9) i c,max i lo,max i in,avg 16 a 0.81 11.44 a 8.3 a (6) i c,min i lo,min i in,avg 12 a 0.81 11.44 a 3.3 a (7) for the two ? phase converter, the input capacitor(s) rms current is then (note: d = 1.655 v/5 v = 0.331):
cs5308 http://onsemi.com 27 i cin,rms [2d (i c,min 2 i c,min i c,in (11) i c,in 2 3) i in,avg 2 (1 2d)] 1 2 [0.662 (3.3 2 3.3 5 5 2 3) 11.44 2 (1 0.662)] 1 2 8.94 a rms at this point, the designer must decide between saving board space by using higher ? rated/more costly capacitors or saving cost by using more lower ? rated/less costly capacitors. to save board space, we choose the sp (oscon) series capacitors by sanyo: 680 f, 6.3 v, 4.84 a rms , 13 m , 10 10.5mm. we need approximately 8.94 a/4.84 a = 1.84 or n in = 2 capacitors on the input for a conservative design. 4. input inductor selection the input inductor must limit the input current slew rate to less than 0.1 a/ s during a load transient from 0 to 28 a. a conservative value will be calculated assuming the minimum number of output capacitors (n out = 5), two input capacitors (n in = 2), worst case esr values for both the input and output capacitors, and a maximum duty cycle (d = (1.825 v + 45 mv av p )/5.0 v in = 0.374). first, use equation 15 to calculate the voltage across the output inductor due to the 28 a load current being shared equally between the two phases: (15) v lo v in v out,no ? load (i o,max 2) esr out n out 5.0 v 1.87 v 14 a 23 m 5 3.194 v second, use equation 16 to determine the rate of current increase in the output inductor: di lo dt v lo lo 3.194 v 825 nh 3.872 v s (16) finally, use eq uations 17 and 18 to calculate the minimum input inductance value: v ci esr in n in di lo dt d f sw 13 m 2 3.872 s 0.374 335 khz 28.1 mv (17) li min v ci di in dt max 28.1 mv 0.1 a s 281 nh (18) we choose the small, cost effective t30 ? 26 core from micrometals (33.5 nh/n 2 ) with #16 awg. we need at least 2.89 or 3 turns to achieve the minimum inductance value. with three turns the input inductor will be: l i 3 2 33.5 nh n 2 301 nh this inductor is available as part number ctx15 ? 14771 from coiltronics. figure 26. cs5308 circuitry with only 5 rubycon output capacitors, 2 oscon input capacitors and a 300 nh input inductor. the di in /dt of the input current (0.064 a/ s) is much lower than expected (0.1 a/ s) because of input voltage drop and lower real esrs than specified in the capacitors? data sheets. 5. mosfet & heatsink selection the ntb75n03 ? 06 from on semiconductor is chosen for both the control and synchronous mosfet due to its low r ds(on) and low gate ? charge requirements. the following parameters are derived from the ntb75n03 ? 06 data sheet: r ds(on) = 5.3 m q switch = 29 nc q g = 52 nc q rr = 23 nc q oss = 35 nc (approx.) vf diode = 0.76 v @ 15 a jc = 1.0 c / w cs5308 parameters: i g = 1 a v g = 10 v t_nonoverlap = 65 ns the rms value of the current in the control mosfet is calculated from equation 20 and the previously derived values for d, i lmax , and i lmin at the converter ?s maximum output current:
cs5308 http://onsemi.com 28 0.575 [(16 2 16 12 12 2 ) 3] 1 2 (20) i rms,cntl d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 8.08 a rms equation 19 is used to calculate the power dissipation of the control mosfet: p d,control (i rms,cntl 2 r ds(on) ) (i lo,max q switch i g v in f sw ) (q oss 2 v in f sw ) (v in q rr f sw ) (19) (8.08 2 a rms 5.3 m ) (16 a 29 nc 1a 5v 335 khz) (35 nc 2 5v 335 khz) (5 v 23 nc 335 khz) 0.346 w 0.78 w 0.03 w 0.04 w 1.2 w the rms value of the current in the synchronous mosfet is calculated from equation 27 and the previously derived values for d, i lo,max , and i lo,min at the converter?s maximum output current: (27) i rms,synch 1 d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 0.669 [(16 2 16 12 12 2 ) 3] 1 2 11.5 a rm s equation 26 is used to calculate the power dissipation of the synchronous mosfet: p d,synch (i rms,synch 2 r ds(on) ) (vf diode i o,max 2 t_nonoverlap f sw ) (26) (11.5 2 a rms 5.3 m ) (0.76 v 28 a 2 65 ns 335 khz) 0.70 w 0.23 w 0.93 w equation 28 is used to calculate the heat sink thermal impedances necessary to maintain less than the specified maximum junction temperatures at 60 c ambient: cntl (115 60 c) 1.2 w 1.0 c w 46 c w s yn c h ( 115 60 c ) 0.93 w 1.0 c w 59 c w if board area permits, a cost effective heatsink could be formed by using a to ? 263 mounting pad of at least 1.0 ? 1.5 in 2 per mosfet on a single ? sided, 1 oz. copper pcb (or 0.5 to 0.75 in 2 on each side of a two ? sided board). if board space must be conserved, aavid offers clip ? on heatsinks for to ? 220 thru ? hole packages. examples of these heatsinks include #577002 (1 0.75 0.25 , 39 c/w at 1 w) and #591302 (0.75 0.5 0.5 , 34 c/w at 1 w) 6. adaptive voltage positioning first, to achieve the 335 khz switching frequency, use figure 3 to determine that a 39 k resistor is needed for r osc . then, use figure 4 to find the v fb bias current at the corresponding value of r osc . in this example, the 39 k r osc resistor results in a v fb bias current of approximately 7.0 a. knowing the v fb bias current, one can calculate the required values for r vfbk and r drp using equations 29 through 31. the no ? load position is easily set using equation 29: r vfbk v no ? load ibias vfb +45 mv 7.0 a 6.49 k (29) for inductive current sensing, the designer must calculate the inductor?s resistance (r l ) and approximate any resistance added by the circuit board (r pcb ). we found the inductor?s nominal resistance in section 2 (1.03 m ). in this example, we approximate 0.75 m for the circuit board resistance (r pcb ). with this information, equation 30 can be used to calculate the increase at the v drp pin at full load; v drp i o,max (r l r pcb ) g vdrp 28 a (1.03 m 0.75 m ) 3.2 v v 159 mv (30) r drp can then be calculated from equation 31: r drp v drp (ibias vfb v out,full ? load r vfbk ) 159 mv (7.0 a 45 mv 6.49 k ) 11.5 k (31) 7. current sensing choose the current sense network (r csn , c csn , n = 1 or 2) to satisfy r csn c csn lo (r l r pcb ) (30) the component values determined thus far are l o = 825 nh, r l = 1.03 m , and r pcb = 0.75m . we choose a convenient value for c cs1 (0.01 f) and solve for r cs1 : r csn 825 nh (1.03 m 0.75 m ) 0.01 f 46 k or 50 k when rounded up. after the circuit is constructed, the values of r csn and/or c csn should be tuned to provide a ?square ? wave? at v drp with minimal overshoot and fast rise time due to a step change in load current as shown in figures 19 ? 21. based on experience, the starting value for r csn is probably too low and will need to be increased to provide a current sense signal similar to those in figure 21. equation 30 will be most accurate for higher quality iron powder core materials such as the ? 2 or ? 8 from micrometals. the permeability of these more expensive
cs5308 http://onsemi.com 29 cores is relatively constant versus dc current, ac flux density and frequency. less expensive core materials (such as the ? 52 from micrometals) change their characteristics versus dc current, ac flux density, and frequency . the less expensive materials may yield acceptable converter performance if the current sense time constant is set approximately 2 longer than anticipated. for example, use approximately twice the resistance (r csn ) or twice the capacitance (c csn ) when using the less expensive core material. if we use ? 52 material for this design, the value of r csn should be increased to 2 50 k or 100 k . 8. error amplifier tuning the error amplifier is tuned by adjusting c amp to provide an acceptable full ? load transient response as shown in figures 22 ? 24. after a value for c amp is chosen, the peak ? to ? peak voltage ripple on the comp pin is examined under full ? load to insure less than 20 mv pp as shown in figure 25. 9. current limit setting the maximum inductor resistance, the maximum pcb resistance, and the maximum current ? sense gain as shown in equation 34 determine the current limit. the maximum current, i out,lim , was specified in the design requirements. the maximum inductor resistance occurs at full ? load and the highest ambient temperature. this value was found in the ?output inductor section? (1.58 m ). the pcb resistance increases due to the change in ambient temperature: r pcb,max 0.75 m (1 0.39% c (60 25) c) 0.85 m v ilim (i out,lim i lo 2) (r lmax r pcb,max ) g ilim (33 a 4.0 a 2) (1.29 m 0.85 m ) 6.5 v v 0.486 vdc set the voltage at the i lim pin using a resistor divider from the 3.3 v reference output as shown in figure 27. if the resistor from i lim to gnd is chosen as 1 k (r lim2 ), the resistor from i lim to 3.3 v can be calculated from: r lim1 (v ref v ilim ) (v ilim r lim2 ) (3.3 v 0.486 v) (0.486 v 1k ) 5790 or 5.76 k r lim2 1 k r lim1 ?? 3.3 v ref to i lim pin v lim figure 27. setting the current limit 10. pwm comparator input voltage use equation 35 to check the voltage level to the positive pin of the internal pwm comparators to insure the design will not saturate the comparator at maximum dac output voltage with 1% error, avp at full ? load, 100% duty cycle (d = 1), and maximum internal ramp (310 mv at 100% duty ? cycle): v csref,max max vid setting w avp @ full ? load 1.01 1.825 v 45 mv 1.80 v v con,max (i o,max 2 i lo 2) r max g csa,max (28 a 2 4.0 a 2) (1.29 m 0.82 m ) 3.95 v v 0.133 v v csref,max v con,max 310 mv d 1.80 v 0.133 v 310 mv 2.243 v (35) this value is acceptable because it is below the specified maximum of 2.45 v. 11. vtt pgd delay time setting to obtain the 335 khz switching frequency the value of r osc was set to 39 k in section 6. figure 4 must be used to determine the value of the vtt ct charge current at this r osc value. in this example, the 39 k r osc resistor results in a vtt ct charge current of approximately 26 a. using equation 34 and solving for c vtt : t d,vtt (1 v 0.25 v) c vtt vtt ct _current (34) c vtt t d,vtt vtt ct _current 0.75 v 2.5 ms 26 a 0.75 v 0.086 for0.1 f
cs5308 http://onsemi.com 30 12. soft start time to set the soft start time we first approximate the comp voltage at a duty ? cycle of d = 1.745 v/5 v = 0.349: v comp v out @0a channel_startup_offset int_ramp 1.745 v 0.40 v 250 mv 0.349 2.232 v we then choose a convenient value for r cmp1 (5.62 k ) and solve equation 37 for c cmp2 : c cmp2 t ss i comp (v comp r cmp1 i comp ) 6.5 ms 30 a (2.232 v 5.62 k 30 a) 0.0945 for0.1 f figure 28. timing diagram, vtt power good v tt v tt power good comp/v cc core power good 1 ? 5 ms 50 s comp must be < 0.27 v before powering up
cs5308 http://onsemi.com 31 package dimensions so ? 28l dw suffix case 751f ? 05 issue g a1 1 15 14 28 b s x m 0.025 y s t m 0.25 y m seating plane a dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 g 1.27 bsc h 10.05 10.55 l 0.41 0.90 m 0 8 l c pin 1 ident d e h 0.10 ? x ? ? y ? g ? t ? m notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold protrusion 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable damber pr5otrusion shall not be 0.13 totatl in excess of b dimension at maximum material condition. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 cs5308/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative v 2 is a trademark of switch power, inc. pentium is a registered trademark of intel, corp.

▲Up To Search▲

Price & Availability of CS5308GDWR28

	To Download CS5308GDWR28 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .